发明名称 |
STORAGE DEVICE INCLUDING RANDOM ACCESS MEMORY DEVICES AND NONVOLATILE MEMORY DEVICES |
摘要 |
A storage device includes random access memories, nonvolatile memory devices, a controller configured to control the nonvolatile memory devices, and a driver circuit configured to receive a command and an address from an external device, output a buffer command according to the command and the address, and transmit the command and the address to one of a first channel connected to the random access devices and a second channel connected to the controller according to the command and the address. The storage device further includes a plurality of data buffers configured to communicate with the external device and electrically connect the external device to one of a third channel connected to the random access memory devices and a fourth channel connected to the controller in response to the buffer command. Each of the data buffers includes a FIFO (first-in first-out) circuit. |
申请公布号 |
US2017075829(A1) |
申请公布日期 |
2017.03.16 |
申请号 |
US201615260916 |
申请日期 |
2016.09.09 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE HAN-JU;YOO YOUNGKWANG;CHO YOUNGJIN |
分类号 |
G06F13/16;G06F13/40 |
主分类号 |
G06F13/16 |
代理机构 |
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代理人 |
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主权项 |
1. A storage device comprising:
a plurality of random access memories; a plurality of nonvolatile memory devices; a controller configured to control the nonvolatile memory devices; a driver circuit configured to receive a command and an address from an external device, output a buffer command according to the command and the address, and transmit the command and the address to one of a first channel connected to the random access devices and a second channel connected to the controller according to the command and the address; and a plurality of data buffers configured to communicate with the external device and electrically connect the external device to one of a third channel connected to the random access memory devices and a fourth channel connected to the controller in response to the buffer command, wherein each of the data buffers comprises a first-in first-out (FIFO) circuit. |
地址 |
SUWON-SI KR |