POWER-DENSITY-BASED CLOCK CELL SPACING

摘要

Techniques for power-density-based clock cell spacing and resulting integrated circuits (ICs) are disclosed herein. In one example, the techniques determine power-usage density for different types of clock cells, as power-usage density relates to heat and IR droop. With the power-usage density for each type of clock cell determined, the techniques assign a keep-out region for each type of clock cell that is not fixed for all types of clock cells. These regions are instead based on the heat and IR droop corresponding to estimated power-usage density for each type of clock cell. Clock cells are then placed in a layout of an IC. The resulting IC has clock cells spaced sufficiently to reduce heat and IR droop while concurrently having excellent timing closure and performance.

主权项

1. An integrated circuit comprising:
multiple clock cells of a first type having a first keep-out region, the first type having a first power-usage density; multiple clock cells of a second type having a second keep-out region, the second type having a second power-usage density, the first and the second power-usage densities being different, a higher of the first and second power-usage densities having a larger keep-out region than a lower of the first and second power-usage densities; and a layout of the multiple clock cells of the first type and the second type on the integrated circuit, the layout separating the multiple clock cells of the first type and second type such that the respective keep-out regions of the respective clock cells do not overlap.