HIGH-SPEED PROGRAMMABLE CLOCK DIVIDER

摘要

Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.

主权项

1. A programmable clock divider for receiving an input clock signal at an input frequency and producing an output clock signal at an output frequency, the ratio of the input frequency to the output frequency set by a programmable divide ratio, the programmable clock divider comprising:
a modulo N counter configured to produce a count signal that counts modulo the programmable divide ratio; a half-rate clock signal generator configured to produce a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that each toggle at one-half the rate of the output clock signal; a first exclusive OR gate having inputs coupled to the common half-rate clock signal and the even half-rate clock signal and an output driving an even clock signal; a second exclusive OR gate having inputs coupled the common half-rate clock signal and the odd half-rate clock signal and an output driving an even clock signal; and a selector configured to produce the output clock signal by selecting the even clock signal when the programmable divide ratio is even and selecting the odd clock signal when the programmable divide ratio is odd.