发明名称 |
Flash Memory System Using Complementary Voltage Supplies |
摘要 |
A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells. |
申请公布号 |
US2017076809(A1) |
申请公布日期 |
2017.03.16 |
申请号 |
US201615361473 |
申请日期 |
2016.11.27 |
申请人 |
Silicon Storage Technology, Inc. |
发明人 |
Tran Hieu Van;Ly Anh;Vu Thuan;Nguyen Hung Quoc |
分类号 |
G11C16/30;H01L27/115;G11C16/04;G11C16/14;G11C16/26 |
主分类号 |
G11C16/30 |
代理机构 |
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代理人 |
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主权项 |
1. A method of operating a flash memory device comprising a first set of memory cells and a second set of memory cells, the method comprising:
erasing the first set of memory cells, the erasing step comprising: applying a first negative voltage to each coupling gate of the first set of memory cells; applying a non-negative voltage to each word line and bit line of the first set of memory cells; and applying a first positive voltage to each erase gate of the first set of memory cells; and inhibiting the erasing of the second set of memory cells by applying a second positive voltage to each coupling gate of the second set of memory cells. |
地址 |
San Jose CA US |