发明名称 CHIP PACKAGING METHOD
摘要 A chip packaging method, comprising the following steps: S1, providing a carrier (1), and forming a bonding layer (2) on a surface of the carrier (1); S2, forming a first dielectric layer (3) on a surface of the bonding layer (2), and forming, in the first dielectric layer (3), a plurality of first through holes (4) corresponding to electric leads of a semiconductor chip (5); S3, attaching the semiconductor chip (5) facedown to a surface of the first dielectric layer (3); S4, forming a plastic package layer (6) covering the chip on the surface of the first dielectric layer (3); S5, separating the bonding layer (2) from the first dielectric layer (3), so as to remove the carrier (1) and the bonding layer (2); and S6, forming a redistribution layer (7) for the semiconductor chip (5) based on the first dielectric layer (3) and the first through holes (4). By means of the method, the problem that the semiconductor chip (5) is contaminated due to direct bonding of the bonding layer (2) and the semiconductor chip (5) is not only avoided, but also the problem of having difficulty in forming through holes in the first dielectric layer (3) after the chip is bonded is solved. The method is simple in processing steps and can effectively improve the product yield and electrical properties.
申请公布号 WO2017041519(A1) 申请公布日期 2017.03.16
申请号 WO2016CN82779 申请日期 2016.05.20
申请人 SJ SEMICONDUCTOR (JIANGYIN) CORPORATION 发明人 QIU, Yuedong;LIN, Chengchung
分类号 H01L21/60 主分类号 H01L21/60
代理机构 代理人
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