Dual Path Source Synchronous Interface

摘要

A dual path source synchronous interface is disclosed. In one embodiment, a source synchronous interface includes a transmitter coupled to serially receive data from a first functional circuit block, and a receiver coupled to provide data serially to a second functional circuit block. Data is conveyed to the transmitter on a single signal line, and similarly, from the receiver on another single signal line. The transmitter is coupled to the receiver by two signal lines. The serial data received by the transmitter may be separated into two streams of alternating bits, e.g., a first bit is transmitted on one signal line, the next bit is transmitted on the other signal line, and so forth. At the receiver, the alternating bit streams may be re-combined into a single bit stream for transfer to the second functional circuit.

主权项

1. An integrated circuit comprising:
first and second functional circuit blocks, wherein the first and second functional circuit blocks are coupled to one another by a source synchronous interface, wherein the source synchronous interface includes:
a clock transmitter configured to transmit a first clock signal from the first functional circuit block to the second functional circuit block;a first data transmitter configured to, responsive to a rising edge of the first clock signal, transmit data across a first signal path from the first functional circuit block to a receiver in the second functional circuit block, wherein the receiver is configured to latch data received from the first signal path responsive to receiving a falling edge of the first clock signal;a second data transmitter configured to, responsive to a falling edge of the first clock signal, transmit data across a second signal path from the functional circuit block to receiver in the second functional circuit block, wherein the receiver is configured to latch data received from the second signal path responsive to receiving the rising edge of the first clock signal;wherein the first and second data transmitters are both coupled to receive data serially via a third data path in the first functional circuit block, and wherein the first and second signal paths are separate from one another.