发明名称 |
SOLID-STATE IMAGE PICKUP ELEMENT, AND IMAGE PICKUP SYSTEM |
摘要 |
Provided is a solid-state image pickup element including: a plurality of pixels arranged in a pixel well region; a readout circuit arranged in a peripheral well region, having a first input terminal for receiving the pixel signals from the plurality of pixels and a second input terminal for receiving a reference signal; and a reference signal circuit arranged in the peripheral well region, having a first electrode to which a ground voltage is supplied, and being configured to output the reference signal to the second input terminal of the readout circuit, wherein a resistance value R1 of an electrical path from one of a plurality of pixel well contacts to the first electrode and a resistance value R2 of an electrical path from one of a plurality of peripheral well contacts closest to the first electrode to the first electrode satisfy a relationship of R1<R2. |
申请公布号 |
US2017078603(A1) |
申请公布日期 |
2017.03.16 |
申请号 |
US201615227576 |
申请日期 |
2016.08.03 |
申请人 |
CANON KABUSHIKI KAISHA |
发明人 |
Yamasaki Takahiro;Minowa Masaaki;Ota Keisuke;Sakuragi Takamasa;Kaifu Noriyuki;Koizumi Toru;Saito Kazuhiro;Kobayashi Daisuke |
分类号 |
H04N5/378;H01L27/146 |
主分类号 |
H04N5/378 |
代理机构 |
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代理人 |
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主权项 |
1. A solid-state image pickup element, comprising:
a semiconductor substrate including a pixel well region and a peripheral well region; a pixel ground wiring arranged on the pixel well region; a peripheral ground wiring arranged on the peripheral well region; a plurality of pixel well contacts connecting the pixel ground wiring and the pixel well region; a plurality of peripheral well contacts connecting the peripheral ground wiring and the peripheral well region; a plurality of pixels arranged in the pixel well region in a plurality of columns, each of the plurality of pixels being configured to output a pixel signal; a readout circuit arranged in the peripheral well region, the readout circuit including a first input terminal configured to receive the pixel signal from each of the plurality of pixels and a second input terminal configured to receive a reference signal; a reference signal circuit arranged in the peripheral well region, the reference signal circuit including a first electrode to which a ground voltage is supplied, and being configured to output the reference signal to the second input terminal of the readout circuit; and a wiring connecting the first electrode of the reference signal circuit and the pixel ground wiring, wherein a resistance value R1 of an electrical path from one of the plurality of pixel well contacts to the first electrode and a resistance value R2 of an electrical path from one of the plurality of peripheral well contacts closest to the first electrode to the first electrode satisfy a relationship of R1<R2. |
地址 |
Tokyo JP |