发明名称 |
VARIABLE RESISTANCE MEMORY |
摘要 |
According to one embodiment, a variable resistance memory includes first and second semiconductor regions in a layer; a memory cell on the first semiconductor region, the memory cell including a first transistor having a first gate connected to a word line and a memory element, the word line extending in a first direction parallel to a surface of the layer; and a second transistor on the second semiconductor region and connected to the memory cell via a bit line, the bit line extending a second direction parallel to the surface of the layer, and the second direction intersecting the first direction. The second semiconductor region extends in a third direction parallel to the surface of the substrate and the third direction intersects the first and second directions. |
申请公布号 |
US2017077175(A1) |
申请公布日期 |
2017.03.16 |
申请号 |
US201615065506 |
申请日期 |
2016.03.09 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
UEDA Yoshihiro |
分类号 |
H01L27/22;H01L43/08;H01L23/528;H01L43/02 |
主分类号 |
H01L27/22 |
代理机构 |
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代理人 |
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主权项 |
1. A variable resistance memory comprising:
first and second semiconductor regions provided in a semiconductor layer; a first memory cell provided on the first semiconductor region, the first memory cell including a first transistor and a first memory element, the first transistor having a first gate connected to a word line, the word line extending in a first direction parallel to a surface of the semiconductor layer; and a second transistor provided on the second semiconductor region and connected to one end of the first memory cell via a first bit line, the first bit line extending a second direction parallel to the surface of the semiconductor layer, and the second direction intersecting the first direction, wherein the second semiconductor region extends in a third direction parallel to the surface of the semiconductor layer and the third direction intersects the first and second directions. |
地址 |
Tokyo JP |