FinFET Memory Device

摘要

A FinFET system comprises a first inverter comprising a first p-type pull-up transistor (PU) and a first n-type pull-down transistor (PD connected in series with the first PD, a second inverter cross-coupled to the first inverter comprising a second PU and a second PD connected in series with the second PD, a first pass-gate transistor, wherein the first pass-gate transistor is coupled between the first inverter and a first bit line, a second pass-gate transistor, wherein the second pass-gate transistor is coupled between the second inverter and a second bit line, a first dummy transistor coupled to a first common node of the first PU and the first PD and a second dummy transistor coupled to a second common node of the second PU and the second PD.

主权项

1. A system comprising:
a first inverter comprising:
a first p-type pull-up transistor (PU); anda first n-type pull-down transistor (PD), wherein the first PU is connected in series with the first PD; a second inverter cross-coupled to the first inverter comprising:
a second PU; anda second PD, wherein the second PU is connected in series with the second PD; a first pass-gate transistor, wherein the first pass-gate transistor is coupled between the first inverter and a first bit line; a second pass-gate transistor, wherein the second pass-gate transistor is coupled between the second inverter and a second bit line; a first dummy transistor coupled to a first common node of the first PU and the first PD, wherein a source and a gate of the first dummy transistor is connected together and further connected to the first common node; and a second dummy transistor coupled to a second common node of the second PU and the second PD, wherein a source and a gate of the second dummy transistor is connected together and further connected to the second common node.