发明名称 GATE TURN ON VOLTAGE COMPENSATING CIRCUIT, DISPLAY PANEL, DRIVING METHOD AND DISPLAY APPARATUS
摘要 The present disclosure provides a gate turn on voltage compensating circuit, a display panel, a driving method and a display apparatus thereof. The gate turn on voltage compensating circuit includes a voltage generation module, a clock control module and a chamfering module. The voltage generation module is used for correspondingly outputting generated first voltage signal and second voltage signal to a first voltage input terminal and a second voltage input terminal of the chamfering module; the clock control module is used for controlling the chamfering module to output corresponding chamfered voltage signals in the corresponding time periods, so that the chamfering depths of gate turn on voltage signals input correspondingly to respective gate drive chips in different time periods are different.
申请公布号 US2017076657(A1) 申请公布日期 2017.03.16
申请号 US201615086836 申请日期 2016.03.31
申请人 BOE TECHNOLOGY GROUP CO., LTD. ;CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. 发明人 LU Xu;HSU Yih Jen;SHANG Fei;QIU Haijun;XIAO Lijun;HOU Shuai
分类号 G09G3/20;H03K17/687 主分类号 G09G3/20
代理机构 代理人
主权项 1. A gate turn on voltage compensating circuit, comprising a voltage generation module, a clock control module and a chamfering module, the voltage generation module being used for generating a first voltage signal and a second voltage signal and correspondingly outputting, through a first voltage output terminal and a second voltage output terminal thereof, the generated first and second voltage signals to a first voltage input terminal and a second voltage input terminal of the chamfering module; a first output terminal of the clock control module being connected with a first control terminal of the chamfering module, a second output terminal of the clock control module being connected with a second control terminal of the chamfering module, and the clock control module controlling, through time sequence signals output via the first output terminal and the second output terminal thereof, the chamfering module to output corresponding chamfered gate turn on voltage signal in a corresponding time period.
地址 Beijing CN