| 摘要 |
A memory control circuit 10 controls an operation of reading stored data from a memory cell 50 connected to a word line WL and a bit line BL based on an address Address including a row address Ax and a column address Ay. When the address Address includes redundancy addresses P1 to P4 designating a word line WLa or a bit line BLc connected to a specific memory cell Cc, redundancy decoders 13-1 to 13-4 replace the specific memory cell Cc with a redundancy memory cell RCc connected to redundancy word lines RWL1 and RWL2 or redundancy bit lines RBL1 and RBL2. Redundancy address latch circuits 12-1 to 12-4 respectively hold the redundancy addresses P1 to P4, and erase the held redundancy addresses P1 to P4 based on a reset signal RS inputted from the memory control circuit 10. |
