| 摘要 |
<P>PROBLEM TO BE SOLVED: To speed up access time in a multi-port SRAM. <P>SOLUTION: Regarding a P-well region formed with a pair of CMOS inverters and an N-well region that constitute a multi-port SRAM cell, the P-well region is divided into two P-well regions PW1, PW2. These two P-well regions are formed on the two sides of the N-well region NW, so that the boundaries between the regions are parallel to bit lines. A pair of access gates N3, N5 and a pair of access gates N4, N6 are formed in the two divided P-well regions, respectively. Thus, the bit lines can be made shorter, and the wiring capacity can be reduced. <P>COPYRIGHT: (C)2011,JPO&INPIT |
