发明名称 配線基板
摘要 A wiring board includes an insulating layer having a lower layer conductor on a lower surface thereof, a plurality of semiconductor element connection pads arranged in a lattice pattern in a semiconductor element mounting portion 1a having a quadrangular shape on the insulating layer, a via hole formed in the insulating layer below each of the semiconductor element connection pads, and a via conductor filled in the via hole and formed integrally with each of the semiconductor element connection pads. The wiring board includes a reinforcing via hole formed in the insulating layer in an outer region outside an arrangement region of the semiconductor element connection pads in corner portions of the semiconductor element mounting portion, and a reinforcing via conductor formed in the reinforcing via hole.
申请公布号 JP6096640(B2) 申请公布日期 2017.03.15
申请号 JP20130226097 申请日期 2013.10.31
申请人 京セラ株式会社 发明人 飯野 正和;藤崎 昭哉;大吉 隆文
分类号 H05K1/02;H01L23/12;H05K3/46 主分类号 H05K1/02
代理机构 代理人
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