| 摘要 |
A time-to-digital converter device includes a first delay chain circuit that generates a first value corresponding to a time delay between a start signal and a stop signal. The time-to-digital converter device also includes at least one second delay chain circuits that generates a second value corresponding to a time delay between a delayed start signal and the stop signal. At least one delay element generates the delayed start signal by applying a predetermined delay to the start signal, and a combining circuit generates an output value based on the first and second values. In the time-to-digital converter according to the exemplary embodiments of the present advancements, the output value corresponds to the time delay between the start signal and the stop signal. |
