| 摘要 |
A method (600, 800) and apparatus (100) for detecting a latent slow bit (e.g., a latent slow-to-erase bit) (306) in a non-volatile memory (NVM) (101) is disclosed. A maximum number of soft program pulses among addresses during an erase cycle is counted (602, 815). In accordance with at least one embodiment, a number of erase pulses during the erase cycle is counted (602, 805). In accordance with various embodiments, determinations are made as to whether the maximum number of the soft program pulses has increased at a rate of at least a predetermined minimum rate comparing to a previous erase cycle (604, 812, 819), whether the maximum number of the soft program pulses has exceeded a predetermined threshold (603, 811, 818), whether the number of erase pulses has increased comparing to a previous erase cycle (603, 811, 818), or combinations thereof. In response to such determinations, the NVM is either passed (606, 823) or failed (605,813, 820) on the basis of the absence or presence of a slow bit in the NVM. |
