| 摘要 |
This arithmetic processing device has: a dynamic voltage and frequency scaling (DVFS) table in which multiple operating frequencies and supply voltage values used for DVFS control are set; a critical path monitoring (CPM) circuit for detecting a delay variation in accordance with a variation in supply voltage; and a control circuit for controlling operations for configuring the DVFS table. The control circuit calibrates the CPM circuit by setting measured operating frequencies and supply voltage values in the table, adjusts supply voltage values corresponding to unmeasured operating frequencies in the table by using the calibrated CPM circuit, and sets the adjusted supply voltage values in the table. Consequently, an increase in testing time is suppressed, and the DVFS control is performed using appropriate supply voltage values in accordance with process variations. |
