发明名称 半導体装置
摘要 A period (inverted period) in which a high negative potential is applied to a gate of the transistor is provided between a writing period and a retention period. In the inverted period, supply of positive electric charge from the drain of the transistor to the oxide semiconductor layer is promoted. Thus, accumulation of positive electric charge in the oxide semiconductor layer or at the interface between the oxide semiconductor layer and a gate insulating film can converge in a short time. Therefore, it is possible to suppress a decrease in the positive electric charge in the node electrically connected to the drain of the transistor in the retention period after the inverted period. That is, the temporal change of data stored in the semiconductor device can be suppressed.
申请公布号 JP6093894(B2) 申请公布日期 2017.03.08
申请号 JP20160082632 申请日期 2016.04.18
申请人 株式会社半導体エネルギー研究所 发明人 鎌田 康一郎
分类号 H01L21/8242;H01L27/108 主分类号 H01L21/8242
代理机构 代理人
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