发明名称 画像処理回路及び画像検出装置
摘要 Each second selection circuit selects, out of a plurality of evaluation values, an evaluation value being in a predetermined relative positional relation with a first evaluation value as an evaluation value outputted from a first selection circuit, and outputs the selected value. The predetermined relative positional relations are different from one another among a plurality of second selection circuits. Every time a second evaluation value is outputted from the second selection circuit corresponding to the integration circuit, the integration circuit reads a weigh value corresponding to a combination of the second evaluation value and the first evaluation, which makes a pair with the second evaluation and is outputted from the first selection circuit, from a storage circuit corresponding to the second selection circuit and integrates the read values. An addition circuit at least adds a plurality of integrated values outputted from a plurality of integration circuits, and an addition value obtained thereby becomes a probability value.
申请公布号 JP6093221(B2) 申请公布日期 2017.03.08
申请号 JP20130072401 申请日期 2013.03.29
申请人 株式会社メガチップス 发明人 山村 尚嗣
分类号 G06T1/00;G06T7/00 主分类号 G06T1/00
代理机构 代理人
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