Voltage regulator with extended minimum to maximum load current ratio

摘要

Voltage regulator with extended minimum to maximum current ratio. In some embodiments, a low-dropout (LDO) voltage regulator disposed within a semiconductor package may include an inner loop; and an outer loop coupled to the inner loop, wherein: the inner loop is configured to control a load response of the LDO voltage regulator and to reduce at least one of: a printed circuit board (PCB) effect on the outer loop, a packaging effect on the outer loop, or a parasitic effect on the outer loop; the outer loop is configured to control a voltage at an output of the LDO voltage regulator; the output of the LDO voltage regulator is coupled to an integrated circuit within the semiconductor package; and the PCB, package, and parasitic effects comprise inductive or resistive effects caused by elements disposed outside of the semiconductor package.

主权项

1. A low-dropout (LDO) voltage regulator disposed within a semiconductor package, the LDO voltage regulator comprising:
an inner loop; and an outer loop coupled to the inner loop, wherein:
the inner loop is configured to control a load response of the LDO voltage regulator and to reduce at least one of: a printed circuit board (PCB) effect on the outer loop, a packaging effect on the outer loop, or a parasitic effect on the outer loop, wherein the inner loop comprises an operational transconductance amplifier (OTA) circuit having a load current dependent DC gain, and wherein the OTA circuit comprises:
an OTA;a tracking pole diode coupled to the OTA, wherein the tracking pole diode is configured to compensate gain variations due to load changes at the output of the OTA circuit; anda filter array coupled in parallel with the tracking pole diode, wherein the filter array is configured to maintain a consistent frequency response under influence of the at least one of the PCB, packaging, or parasitic effect, and wherein the tracking pole diode has: (a) its source terminal coupled to a first terminal of the filter array, and (b) its gate terminal coupled to its drain terminal and to a second terminal of the filter array;the outer loop is configured to control a voltage at an output of the LDO voltage regulator;the output of the LDO voltage regulator is coupled to an integrated circuit within the semiconductor package; andthe PCB, package, and parasitic effects comprise inductive or resistive effects caused by elements disposed outside of the semiconductor package.