发明名称 Method of operating smart card and method of operating smart card system including the same
摘要 A smart card may include data storage and transmission circuitry, a plurality of voltage controllers to supply operational power to card circuitry, a plurality of oscillators to supply an internal clock for the card, and power management circuitry. The power management circuitry may be configured to shut down the oscillators and at least one, but not all, voltage controllers during a period after a data transmission is completed.
申请公布号 US9589221(B2) 申请公布日期 2017.03.07
申请号 US201514819565 申请日期 2015.08.06
申请人 Samsung Electronics Co., Ltd. 发明人 Cho Hyuck-Jun;Na Donald;Baek Seung-Hwan;Oh Jae-Keun;Chun Kee-Moon
分类号 G06F1/06;G06K19/07;G06Q20/34;G06F1/32;G06F1/00 主分类号 G06F1/06
代理机构 Onello & Mello LLP 代理人 Onello & Mello LLP
主权项 1. A method of operating a smart card comprising: deactivating, by a power management unit, a plurality of sub-units based on a plurality of enable signals during a first idle time interval, a first stop signal set to a second logic level and a second stop signal set to a first logic level during the first idle time interval after data transmission is completed, the second stop signal being generated from a frequency detector based on an external clock signal; controlling, by the power management unit and the frequency detector, voltages based on a control signal and level control signals during a clock stop time interval, the voltages being provided to the sub-units, the control signal being generated from the frequency detector, the level control signals being generated from the power management unit based on the control signal, the first stop signal set to the second logic level and the second stop signal set to the second logic level based on the external clock signal during the clock stop time interval after the first idle time interval; and activating, by the power management unit, the plurality of sub-units based on the plurality of enable signals during a second idle time interval, the first stop signal set to the second logic level and the second stop signal set to the first logic level based on the external clock signal during the second idle time interval after the clock stop time interval.
地址 KR