Scalable meta-data objects

摘要

A method is disclosed for defining an integrated circuit. The method includes generating a digital data file that includes both electrical connection information and physical topology information for a number of circuit components. The method also includes operating a computer to execute a layout generation program. The layout generation program reads the electrical connection and physical topology information for each of the number of circuit components from the digital data file and automatically creates one or more layout structures necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file. The computer is also operated to store the one or more layout structures necessary to form each of the number of circuit components in a digital format on a computer readable medium.

主权项

1. A method for defining an integrated circuit, comprising:
obtaining a physical layout of the integrated circuit, wherein obtaining the physical layout of the integrated circuit includes generating a digital data file that includes electrical connection information and physical topology information for transistors that define the integrated circuit, wherein each transistor within the integrated circuit has a corresponding linear-shaped gate electrode structure oriented to extend lengthwise in a first direction, wherein the electrical connection information for each transistor includes an identification of an electrical node to which a gate terminal of the transistor is connected, and an identification of an electrical node to which a source terminal of the transistor is connected, and an identification of an electrical node to which a drain terminal of the transistor is connected, and wherein the physical topology information for each transistor includes a transistor width as measured in the first direction, and a transistor length as measured in a second direction perpendicular to the first direction, and a transistor center horizontal position, and a transistor center vertical position, and wherein obtaining the physical layout of the integrated circuit includes executing a layout generator on a computer to generate a physical layout of the integrated circuit based on the electrical connection information and physical topology information for transistors included in the digital data file, wherein the layout generator is configured to determine which one of multiple interconnect structure options is appropriate for implementation in the physical layout based on switches or parameters in the digital data file, and wherein obtaining the physical layout of the integrated circuit includes recording data defining the physical layout of the integrated circuit on a non-transitory computer readable storage medium in a format suitable for fabrication of the integrated circuit; and utilizing the physical layout of the integrated circuit to fabricate the integrated circuit.