发明名称 Phase-lock assistant circuitry
摘要 Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.
申请公布号 USRE46336(E1) 申请公布日期 2017.03.07
申请号 US201414120258 申请日期 2014.05.14
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 Lin Chih-Chang;Chern Chan-Hong;Swei Steven;Huang Ming-Chieh;Yang Tien-Chun
分类号 H03D13/00;H03L7/06;H03L7/08;H03L7/081;H03L7/087 主分类号 H03D13/00
代理机构 Hauptman Ham, LLP 代理人 Hauptman Ham, LLP
主权项 1. A method for a circuit having a phase lock assistant circuit that receives an input signal and a feedback clock signal having a first phase, a second phase, a third phase, a fourth phase, and fifth phase, and a sixth phase corresponding to a first phase clock, a second phase clock, a third phase clock, a fourth phase clock, a fifth phase clock, and a sixth phase clock, respectively, the method comprising: using the first phase clock, the third phase clock and the fifth phase clock to sample the input signal and generate a first relationship between the feedback clock signal and the input signal and a second relationship between the feedback clock signal and the input signal; using the second phase clock, the fourth phase clock, and the sixth phase clock to sample the input signal and generate a third relationship between the feedback clock signal and the input signal and a fourth relationship between the feedback clock signal and the input signal; and generating a fifth relationship between the feedback clock signal and the input signal based on the first relationship, the second relationship, the third relationship and the fourth relationship; wherein the first phase, the second phase, the third phase, the fourth phase, the fifth phase and the sixth phase are in an order of phase degree.
地址 TW
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