Interconnect structures for wafer level package and methods of forming same

摘要

Representative methods are disclosed for fabricating device packages having a plurality of dies, a molding compound extending along sidewalls of the plurality of dies, and a polymer layer over and contacting the molding compound. The molding compound comprises a non-planar top surface, and a total thickness variation (TTV) of a top surface of the polymer layer is less than a TTV of the non-planar top surface of the molding compound. The device package further includes a conductive feature on the polymer layer, wherein the conductive feature is electrically connected at least one of the plurality of dies.

主权项

1. A method of forming a device package, the method comprising:
disposing a plurality of dies on a carrier; forming a molding compound over the carrier and around the plurality of dies, the molding compound comprising a non-planar top surface between adjacent dies of the plurality of dies; covering the plurality of dies with a first film layer while forming the molding compound; covering the plurality of dies with a polymer layer, the polymer layer contacting the non-planar top surface of the molding compound; planarizing a top surface of the polymer layer to have a total thickness variation (TTV) less than a TTV of the non-planar top surface of the molding compound; and forming a conductive line on the polymer layer.