发明名称 |
Parallel and serial data with controller, delay, and register circuits |
摘要 |
The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. |
申请公布号 |
US9588178(B2) |
申请公布日期 |
2017.03.07 |
申请号 |
US201615075950 |
申请日期 |
2016.03.21 |
申请人 |
Texas Instruments Incorporated |
发明人 |
Whetsel Lee D. |
分类号 |
G01R31/3177;G06F1/12;G06F13/28;G06F13/42;G01R31/3185;G01R31/28;H03K19/0175 |
主分类号 |
G01R31/3177 |
代理机构 |
|
代理人 |
Bassuk Lawrence J.;Brill Charles A.;Cimino Frank D. |
主权项 |
1. An integrated circuit comprising:
(a) a data input bus, a data output bus, a serial data input, and a serial data output; (b) a multiplexer having a first input connected to the data input bus, a second input connected to the serial data input, a third input, an output, a first control input, and a second control input; (c) a first flip-flop having an input connected to the output of the multiplexer, a clock input, and having an output connected to the data output bus and connected to the third input of the multiplexer; (d) controller circuitry having a first control output coupled to the first control input of the multiplexer, a second control output coupled to the second control input of the multiplexer, and a control clock output coupled to the clock input of the first flip-flop; (e) a delay circuit having an input coupled to the control clock output and having a delay clock output; and (f) a second flip-flop having an input coupled to the output of the first flip-flop, a clock input coupled to the delay clock output, and an output coupled to the serial data output. |
地址 |
Dallas TX US |