Instruction and logic for multiplier selectors for merging math functions

摘要

A processor includes a front end with logic to identify a multiplier, multiplicand, and mathematical mode based upon an instruction. The processor also includes a multiplier circuit to apply Booth encoding to multiply the multiplier and multiplicand. The multiplier circuit includes circuitry to determine leftmost and rightmost partial products of multiplying the multiplier and multiplicand using Booth encoding. The circuitry includes a most significant bit (MSB) array and least significant bit (LSB) array corresponding to the multiplier. The multiplier circuit also includes logic to selectively enable selectors of the circuitry to find partial products based upon the mathematical mode of the instruction.

主权项

1. A processor, comprising:
a front end including circuitry to:
decode an instruction;identify a multiplier to be multiplied with a multiplicand based on the instruction and a mathematical mode of the instruction; and a multiplier circuit including:
circuitry to apply Booth encoding to multiply the multiplier and multiplicand;a first selector circuit to determine a first plurality of partial products of multiplying the multiplier and multiplicand using Booth encoding, the first selector circuit including a most significant bit (MSB) array and least significant bit (LSB) array corresponding to the multiplier;a second selector circuit to determine a second plurality of partial products of multiplying the multiplier and multiplicand using Booth encoding, the second selector circuit including a most significant bit (MSB) array and least significant bit (LSB) array corresponding to the multiplier; andcircuitry to find partial products based upon the mathematical mode of the instruction by selectively enabling at least one of:
the MSB array of the first selector circuit;the LSB array of the first selector circuit;the MSB array of the second selector circuit; andthe LSB array of the second selector circuit.