| 发明名称 | Phase error detection in phase lock loop and delay lock loop devices | ||
| 摘要 | A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin. | ||
| 申请公布号 | US9590643(B2) | 申请公布日期 | 2017.03.07 |
| 申请号 | US201514940644 | 申请日期 | 2015.11.13 |
| 申请人 | INTERNATIONAL BUSINESS MACHINES CORPORATION | 发明人 | Stanton John W.;Thiagarajan Pradeep |
| 分类号 | G01R25/00;H03L7/095;H03K5/24 | 主分类号 | G01R25/00 |
| 代理机构 | Roberts Mlotkowski Safran Cole & Calderon, P.C. | 代理人 | Meyers Steven;Calderon Andrew M.;Roberts Mlotkowski Safran Cole & Calderon, P.C. |
| 主权项 | 1. A method of lock detection comprising, using an analog circuit to: convert a reference clock to a reference triangle wave;convert a feedback clock to a feedback triangle wave;determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; andgenerate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin. | ||
| 地址 | Armonk NY US | ||