发明名称 |
Thin-film transistor array substrate, manufacturing method therefor and display device thereof |
摘要 |
A thin-film transistor array substrate is disclosed. The array substrate includes a support substrate, a plurality of scan lines on the support substrate, and a plurality of data lines on the support substrate, where the plurality of scan lines are insulated and intersect with the plurality of data lines. The array substrate also includes a plurality of pixel units located near intersections of the scan lines and the data lines, a first metal layer on the support substrate, and an insulating layer on the first metal layer, where the insulating layer includes a plurality of via holes, each exposing a portion of the first metal layer. The array substrate also includes a semiconductor layer on the insulating layer and electrically connected to the first metal layer, and a second metal layer on the semiconductor layer and electrically connected to the semiconductor layer. |
申请公布号 |
US9589990(B2) |
申请公布日期 |
2017.03.07 |
申请号 |
US201514749585 |
申请日期 |
2015.06.24 |
申请人 |
SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.;TIANMA MICRO-ELECTRONICS CO., LTD. |
发明人 |
Zhai Yingteng;Wu Yong |
分类号 |
H01L27/12;H01L29/786;H01L21/4757;H01L29/423 |
主分类号 |
H01L27/12 |
代理机构 |
Alston & Bird LLP |
代理人 |
Alston & Bird LLP |
主权项 |
1. A thin-film transistor array substrate comprising:
a substrate; a plurality of scan lines on the substrate; a plurality of data lines on the substrate, wherein the plurality of scan lines are insulated and intersect with the plurality of data lines, and a plurality of pixel units are located near the intersections of the scan lines and the data lines; a gate electrode metal layer on the substrate; an insulating layer on the gate electrode metal layer, wherein the insulating layer comprises a via hole exposing a portion of the gate electrode metal layer; a semiconductor layer on the insulating layer wherein a portion of the semiconductor layer fills the via hole and contacts the gate electrode metal layer; and a source/drain electrode metal layer on the semiconductor layer, wherein the source/drain electrode metal layer fills the via hole partially by a patterning process using the semiconductor layer as an etch stop layer, wherein the gate electrode metal layer, the semiconductor layer and the source/drain electrode metal layer overlap at least partially. |
地址 |
Shanghai CN |