Techniques for inter-component communication based on a state of a chip select pin

摘要

Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

主权项

1. An apparatus comprising:
a status register; a clock (CLK) pin; a plurality of input/output (I/O) pins [n:0]; a chip select pin; and a logic unit to cause a pin to output an alert event when the chip select pin is in a first state and hold a state of the pin that output the alert event until assertion of the chip select pin, wherein
the logic unit is to receive a command from at least one of the I/O pins in response to the alert event andthe logic unit is to cause transmission of a response using at least one of the I/O pins in response to receipt of the command.