发明名称 |
Methods of fabricating semiconductor devices |
摘要 |
Semiconductor devices and methods of fabricating semiconductor devices are provided. The methods may include forming an interlayer insulation layer on a substrate. The interlayer insulation layer may surround a dummy silicon gate and may expose a top surface of the dummy silicon gate. The methods may also include recessing a portion of the interlayer insulation layer such that a portion of the dummy silicon gate protrudes above a top surface of the recessed interlayer insulation layer and forming an etch stop layer on the recessed interlayer insulation layer. A top surface of the etch stop layer may be coplanarly positioned with the top surface of the dummy silicon gate. The methods may further include forming a trench exposing the substrate by removing the dummy silicon gate using the etch stop layer as a mask. |
申请公布号 |
US9590073(B2) |
申请公布日期 |
2017.03.07 |
申请号 |
US201514815225 |
申请日期 |
2015.07.31 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Ryu Yeon-Tack;Kim Ho-Young;Oh Myoung-Hwan;Yoon Bo-Un;Yim Jun-Hwan |
分类号 |
H01L21/00;H01L29/66;H01L29/49;H01L29/51;H01L21/8234;H01L21/768 |
主分类号 |
H01L21/00 |
代理机构 |
Myers Bigel, P.A. |
代理人 |
Myers Bigel, P.A. |
主权项 |
1. A method of fabricating a semiconductor device, the method comprising:
forming an interlayer insulation layer on a substrate, the interlayer insulation layer surrounding a dummy silicon gate and exposing a top surface of the dummy silicon gate; recessing a portion of the interlayer insulation layer to form a recessed interlayer insulation layer, a portion of the dummy silicon gate protrudes above a top surface of the recessed interlayer insulation layer; forming an etch stop layer on the recessed interlayer insulation layer, a top surface of the etch stop layer being coplanarly positioned with the top surface of the dummy silicon gate; forming a trench exposing the substrate by removing the dummy silicon gate using the etch stop layer as a mask; forming a lower electrode layer along the top surface of the etch stop layer and side surfaces and a bottom surface of the trench; forming an upper electrode layer on the lower electrode layer, the upper electrode layer filling the trench and covering the top surface of the recessed interlayer insulation layer; planarizing the lower electrode layer and the upper electrode layer to expose the etch stop layer; after the exposing of the etch stop layer, removing portions of the lower electrode layer and the upper electrode layer in the trench to form a recess; forming a capping layer filling the recess and covering the top surface of the etch stop layer; and forming a capping pattern in the trench by removing the capping layer on the top surface of the etch stop layer. |
地址 |
KR |