| 主权项 |
1. A logic circuit for computing a modal interval (MI) result value of at least first and second MI functions responsive to respectively, first and second values of a selector signal, the computing based on at least one MI operand value encoded in an operand signal, each MI result or operand value comprising first and second multi-bit set theoretical numbers (STNs) defining first and second end points of a range of real numbers, and further encoding one of the universal and existential quantification values, the logic circuit comprising:
a) first and second arithmetic functional units (AFUs), each connected to receive the operand signal, for performing an arithmetic operation using as arguments therefor each MI operand value encoded in the operand signal, and respectively providing first and second multi-bit STNs encoded in first and second result signals R1 and R2; b) a result register for storing the MI result value, connected to receive the multi-bit STNs respectively provided by the first and second result signals R1 and R2; and, c) a multiplexer having a selector input receiving the selector signal, multi-bit inputs and outputs providing signals encoding multi-bit STNs, and one of the multi-bit inputs or outputs characterized by at least first and second multi-bit ports operationally connected to the first and second AFUs, each port associated with a single selector signal value, said multiplexer causing the first and second multi-bit STNs encoded in the first and second result signals R1 and R2 of the AFU associated with the current selector signal value to be stored in said result register as the MI result value. |
