发明名称 |
Adapting erase cycle parameters to promote endurance of a memory |
摘要 |
In a data storage system including a non-volatile memory array, a controller repeatedly determines at least one health metric of the non-volatile memory array during an operating lifetime of the non-volatile memory array. In response to determining the at least one health metric, the controller selectively varies an erase parameter of the non-volatile memory array over the operating lifetime of the non-volatile memory array, such that endurance of the non-volatile memory array is improved. |
申请公布号 |
US9588702(B2) |
申请公布日期 |
2017.03.07 |
申请号 |
US201414585689 |
申请日期 |
2014.12.30 |
申请人 |
International Business Machines Corporation |
发明人 |
Mittelholzer Thomas;Papandreou Nikolaos;Parnell Thomas;Pozidis Charalampos;Tressler Gary A. |
分类号 |
G11C11/34;G06F3/06;G11C16/34;G06F11/10;G06F11/07;G11C16/14 |
主分类号 |
G11C11/34 |
代理机构 |
|
代理人 |
Russell Brian F.;Bluestone Randall J. |
主权项 |
1. A method in a data storage system including a non-volatile memory array controlled by a controller, the method comprising:
selecting and implementing a first value among a plurality of alternative values as a value of an erase parameter of the non-volatile memory, wherein the selecting includes selecting the first value such that a bit error rate for the non-volatile memory array is greater than that which would be achieved if a second value among the plurality of alternative values for the erase parameter were selected; thereafter, during an operating lifetime of the non-volatile memory array, the controller repeatedly determining at least one health metric of the non-volatile memory array, wherein the at least one health metric includes one based on the bit error rate; and in response to the determining of the at least one health metric, the controller selectively varying the value of the erase parameter of the non-volatile memory array over the operating lifetime of the non-volatile memory array such that the bit error rate is controlled in accordance with a bit error rate threshold greater than the bit error rate, wherein endurance of the non-volatile memory array is improved. |
地址 |
Armonk NY US |