| 发明名称 |
HIGH PERFORMANCE TRANSACTION-BASED MEMORY SYSTEMS |
| 摘要 |
A memory system includes a master controller, an interface with a host computer, and a link bus configured to couple with a slave controller. The master controller includes an address mapping decoder, a transaction queue, and a scheduler. The address mapping decoder is configured to decode address mapping information of a memory device coupled to the slave controller. The scheduler of the master controller is configured to reorder memory transaction requests received from the host computer in the transaction queue using the address mapping information of the memory device. The memory system employs an extended open page policy based on the pending memory transaction requests in the transaction queue of the master controller. |
| 申请公布号 |
US2017060788(A1) |
申请公布日期 |
2017.03.02 |
| 申请号 |
US201514959773 |
申请日期 |
2015.12.04 |
| 申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
CHANG Mu-Tien;ZHENG Hongzhong;YIN Liang |
| 分类号 |
G06F13/16;G06F13/40 |
主分类号 |
G06F13/16 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory system comprising:
a master controller including an address mapping decoder, a transaction queue, and a scheduler; an interface with a host computer; and a link bus configured to couple with a slave controller, wherein the address mapping decoder is configured to decode address mapping information of a memory device coupled to the slave controller, and wherein the scheduler of the master controller is configured to reorder memory transaction requests received from the host computer in the transaction queue using the address mapping information of the memory device. |
| 地址 |
Suwon-si KR |
