METHOD TO FORM STRAINED nFET AND STRAINED pFET NANOWIRES ON A SAME SUBSTRATE

摘要

A semiconductor is provided that includes an nFET gate structure straddling over a first nanowire stack and a portion of a first SiGe layer having a first Ge content. The first nanowire stack comprises alternating layers of a tensily strained silicon layer, and a second SiGe layer having a second Ge content that is greater than the first Ge content and being compressively strained. Portions of the tensily strained silicon layers extend beyond sidewalls surfaces of the nFET gate structure and are suspended. The structure further includes a pFET gate structure straddling over a second nanowire stack and another portion of the first SiGe layer. The second nanowire stack comprises alternating layers of the tensily strained silicon layer, and the second SiGe layer. Portions of the second SiGe layers extend beyond sidewalls surfaces of the pFET gate structure and are suspended.

主权项

1. A method of forming a semiconductor structure, said method comprising:
providing a material stack on a first SiGe layer having a first Ge content, said material stack including alternating layers, and from bottom to top, of a tensily strained silicon layer, and a second SiGe layer having a second Ge content that is greater than the first Ge content and being compressively strained; patterning said material stack and said first SiGe layer to provide a first nanowire stack on a first remaining portion of said first SiGe layer within an nFET device region and a second nanowire stack on a second remaining portion of said first SiGe layer within a pFET device region; forming an nFET gate structure straddling over a portion of said first nanowire stack and a portion of said first remaining portion of said first SiGe layer, and a pFET gate structure straddling over a portion of said second nanowire stack and a portion of said second remaining portion of said first SiGe layer; suspending, in any order, an exposed portion of each tensily strained silicon layer in said nFET device region and an exposed portion of each second SiGe layer in said pFET device region; and forming an epitaxial doped semiconductor material surrounding each suspended portion of said strained silicon layer, and surrounding each suspended portion of said second SiGe layer.