NAND Boosting Using Dynamic Ramping of Word Line Voltages

摘要

Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or a bit cost scalable (BiCS) NAND structure. In some cases, by applying continuous voltage ramping to unselected word lines during or throughout a programming operation, the boosting of channels associated with program inhibited memory cells may be improved. In one example, the slope and timing of a Vpass waveform applied to a group of unselected word lines (e.g., the neighboring word lines of the selected word line) during the programming operation may be set based on the location of the selected word line within the memory array and the locations of the group of unselected word lines within the

主权项

1. An apparatus, comprising:
a set of memory cells; and one or more control circuits configured to determine a programming waveform to be applied to a selected word line connected to a selected memory cell of the set of memory cells and determine a first voltage waveform to be applied to an unselected word line connected to an unselected memory cell of the set of memory cells, the programming waveform includes a voltage ramp to a programming voltage, the first voltage waveform includes a first initial ramp to a first initial voltage and a first final ramp to a pass voltage, the pass voltage is greater than the first initial voltage, the pass voltage is less than the programming voltage, the one or more control circuits configured to cause the programming voltage waveform to be applied to the selected word line and the first voltage waveform to be applied to the unselected word line during a programming operation such that the first final ramp to the pass voltage occurs after the selected word line has been set to the programming voltage.