MEMORY SYSTEM

摘要

A memory system includes first through fifth pins connectable to a host device to output to the host device a first signal through the third pin and to receive from the host device a first chip select signal through the first pin, a second chip select signal through the second pin, a second signal through the fourth pin, and a clock signal through the fifth pin, an interface circuit configured to recognize, as a command, the second signal received through the fourth pin immediately after detecting the first or second chip select signal, and first and second memory cell arrays. The interface circuit and the first and second memory cell arrays are provided in one common package, and is configured to access the first memory cell array when detecting the first chip select signal, and to access the second memory cell array when detecting the second chip select signal

主权项

1. A memory system comprising:
first through fifth pins connectable to a host device to output to the host device a first signal through the third pin and to receive from the host device a first chip select signal through the first pin, a second chip select signal through the second pin, a second signal through the fourth pin, and a clock signal through the fifth pin; an interface circuit configured to recognize, as a command, the second signal received through the fourth pin immediately after detecting the first chip select signal or the second chip select signal; and a first memory cell array and a second memory cell array each comprising memory cells capable of holding data, wherein the interface circuit, the first memory cell array, and the second memory cell array are provided in one common package, and the interface circuit is configured to access the first memory cell array when detecting the first chip select signal, and to access the second memory cell array when detecting the second chip select signal.