| 发明名称 |
DEVICE INCLUDING A SINGLE WIRE INTERFACE AND A DATA PROCESSING SYSTEM HAVING THE SAME |
| 摘要 |
A system including: a master device configured to generate a first signal having a periodic pulse, wherein the first signal includes data; and a slave device including a pin, a delay circuit, a buffer, and a processing circuit, wherein the slave device receives the first signal at the pin, delays the first signal with the delay circuit to generate a second signal having a first delay, delays the first signal with the buffer to generate a third signal having a second delay, and reads the data from the second signal using the third signal at the processing circuit. |
| 申请公布号 |
US2017060791(A1) |
申请公布日期 |
2017.03.02 |
| 申请号 |
US201615190629 |
申请日期 |
2016.06.23 |
| 申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
HUH JUNHO;JANG HORANG;SCHERRER TOMAS;LEE JAEWON |
| 分类号 |
G06F13/16;G11C8/10;G11C7/10;G11C7/22;G06F13/36;G06F13/42 |
主分类号 |
G06F13/16 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A system, comprising:
a master device configured to generate a first signal having a periodic pulse, wherein the first signal includes data; and a slave device including a pin, a delay circuit, a buffer, and a processing circuit, wherein the slave device receives the first signal at the pin, delays the first signal with the delay circuit to generate a second signal having a first delay, delays the first signal with the buffer to generate a third signal having a second delay, and reads the data from the second signal using the third signal at the processing circuit. |
| 地址 |
SUWON-SI KR |
