主权项 |
1. A nano-photonic waveguide comprising of three layers,
a middle layer, a top cladding layer, a bottom cladding layer, and wherein the middle layer having an effective index of refraction higher than those of the top and bottom cladding layers, and regions adjacent to it vertically as well as laterally, said three layers are deposited on a substrate which is selected from Si, Ge, Si-on-Insulator (SOI), Si-on-sapphire (SOS), GaAs, InP, ZnSe, and LiNbO3, said middle waveguide layer serving as the waveguiding layer wherein photons are confined in the transverse and lateral directions by regions selected from one of lower index of refraction, a photonic band gap or photonic crystal structure comprising of two-dimensional or three-dimensional photonic crystal lattice, and wherein two-dimensional photonic crystal structure comprises periodic columns of holes or lower index of refraction regions, said middle layer, serving as the waveguiding layer, is composed of a first layer, a second layer, and a third layer, and wherein the first layer comprises one or more layers of semiconductor selected from Si, Ge, SiGe, II-VI, and III-V, and wherein second layer comprises one or more layers of array of cladded quantum dots, and wherein third layer comprises one or more layers of semiconductor selected from Si, Ge, SiGe, II-VI, and III-V, and wherein said second layer of middle layer comprising of quantum dot array having quantum dots with a core with diameter in the range of 3-6 nm and a cladding of higher energy gap and lower index of refraction material in the range of 0.5-1.5 nm, and wherein said quantum dot core is selected from Si, Ge, combination of Si and Ge, II-VI and III-V semiconductors, and said cladding on quantum dots are selected from SiOx, GeOx, II-VI and III-V materials, and wherein layers of array of cladded quantum dots are deposited on said first layer of middle layer serving as waveguiding layer comprising a semiconductor with p-type conductivity, and the semiconductor layer is selected one from a single crystalline, a poly-crystalline, and an amorphous morphology, and wherein the array of cladded quantum dots is deposited with third layer comprising of semiconductor layer with n-type conductivity, and the semiconductor layer is selected one from a single crystalline, a poly-crystalline, and an amorphous morphology, and wherein the nano-photonic waveguide is formed laterally by removing one or more of columns of holes or low index of refraction regions forming the two-dimensional photonic crystal lattice or photonic bandgap hole lattice, and wherein removal of said columns creates one-dimensional line defects, wherein optical parameters of middle layer serving as the waveguiding layer can be altered by applying an external voltage and associated electric field, and said middle layer optical parameters include one of effective index of refraction, and coefficient of absorption at given light wavelength, and wherein optical parameters are dependent on relative core diameter, cladding thickness and the materials of quantum dots comprising the middle layer, a top cladding layer deposited above the third layer of middle waveguide layer is one selected from SiO2, Si3N4, SiON, and other lower index of refraction and higher energy gap materials, a bottom cladding layer below the first layer of said middle waveguide layer having its material selected from SiO2, Si3N4, SiON, and other lower index of refraction and higher energy gap materials, wherein the first layer of middle waveguide layer is deposited on Si-on-insulator substrate (SOI), and wherein the Si layer in SOI substrate is p+-type crystalline layer, and wherein the insulator layer is SiO2, and wherein the insulator or SiO2 layer is serving as the lower cladding layer, said nano-photonic waveguide structure has a width and a length, and wherein the width is determined by the lines of columns holes or low index of regions missing in the photonic band gap or photonic crystal structure lattice, and wherein the external voltage is applied across the middle waveguide layer via a pair of layers selected from p-type first layer and n-type second layer pair, and p+-type Si crystalline layer of SOI substrate and n-semiconductor layer of third layer of middle waveguide layer pair, wherein the polarity of applied voltage is positive on p+-type Si crystalline layer and negative on n-type second layer. |