Memory device error check and scrub mode and error transparency

摘要

An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

主权项

1. A dynamic random access memory device (DRAM), comprising:
a storage array including multiple memory segments, the memory segments including multiple memory locations to store data and error checking and correction (ECC) information associated with the data; I/O (input/output) circuitry to couple to an associated memory controller, the I/O circuitry to receive a trigger for an error check and scrub (ECS) mode when coupled to the associated memory controller; and an internal controller on the DRAM, responsive to the trigger for the ECS mode, to read one or more memory locations, perform ECC for the one or more memory locations based on the ECC information, and count error information, the error information including a segment count indicating a number of segments having N or more errors, and a maximum count indicating a maximum number of errors in any segment.