CELL GRID ARCHITECTURE FOR FINFET TECHNOLOGY

摘要

A layout of a cell grid comprises a plurality of polycrystalline silicon (POLY) lines in the cell gird, wherein the POLY lines are arranged horizontally and evenly spaced with a pitch X, and a plurality of fin-shaped oxide diffused (OD) regions in the cell gird, wherein the fin-shaped OD regions are arranged vertically and evenly spaced with a pitch Y, wherein the pitch Y of the fin-shaped OD regions defines width of the cell grid. The layout of the cell grid further comprises a plurality of PMOS transistors and NMOS transistors in the cell grid, wherein the PMOS transistors and NMOS transistors have their source nodes and drain nodes formed in the fin-shaped OD regions and their gates connected to the POLY lines, wherein the plurality of PMOS transistors and NMOS transistors are connected together to form one or more CMOS devices in the cell grid.

主权项

1. A layout of a cell grid, comprising:
a plurality of polycrystalline silicon (POLY) lines in the cell gird, wherein the POLY lines are arranged in a first direction and evenly spaced with a first pitch; a plurality of fin-shaped oxide diffused (OD) regions in the cell gird, wherein the fin-shaped OD regions are arranged in a second direction and evenly spaced with a second pitch, wherein the second pitch of the fin-shaped OD regions defines a width of the cell grid; and a plurality of PMOS transistors and NMOS transistors in the cell grid, wherein the plurality of PMOS transistors and NMOS transistors have their source nodes and drain nodes formed in respective ones of the fin-shaped OD regions and their gates connected to respective ones of the POLY lines; wherein the plurality of PMOS transistors and NMOS transistors are connected together to form one or more CMOS devices in the cell grid.