HARD MASK ETCH AND DIELECTRIC ETCH AWARE OVERLAP FOR VIA AND METAL LAYERS

摘要

A method and apparatus for generating a final dielectric etch compensation table and a final hard mask etch compensation table for either OPC or MPC process flows are provided. Embodiments include performing an overlap pattern classification on a wafer; calibrating a dielectric etch bias or a hard mask etch bias based on the pattern classification; comparing either a CD overlap of a via layer with a metal layer and a CD overlap of the via layer with a lower connecting metal layer or a CD overlap of the metal layer with an upper connecting via layer and a CD overlap of the metal layer with the via layer against a criteria; outputting final dielectric etch compensation and hard mask etch compensation tables to either OPC or MPC process flows; and repeating the steps of calibrating, comparing, and outputting for either the via layer or metal layer remaining.

主权项

1. A method comprising:
performing an overlap pattern classification on a wafer; calibrating either a dielectric etch bias or a hard mask etch bias based on the pattern classification; comparing either a top critical dimension (CD) overlap of a via layer with an upper connecting metal layer and a bottom CD overlap of the via layer with a lower connecting metal layer or a top CD overlap of the upper connecting metal layer with an upper connecting via layer and a bottom CD overlap of the upper connecting metal layer with the via layer against a criteria based on the calibration; outputting a final dielectric etch compensation table for the via layer or a final hard mask etch compensation table for the upper connecting metal layer to either an optical proximity correction (OPC) process flow or a mask process correction (MPC) process flow based on the comparison; and repeating the steps of calibrating, comparing, and outputting for either the via layer or the upper metal layer remaining.