DATA PROCESSING SYSTEM WITH SECURE KEY GENERATION

摘要

A method of secure key generation includes writing a predetermined write pattern to a particular address of volatile memory, wherein the volatile memory includes bit lines; reading data from the particular address while applying a first set of operating variables to the volatile memory, subsequent to the writing; sensing a first plurality of timing mismatches during the reading, wherein sense amplifiers are coupled to the bit lines, each latch of a plurality of latches is coupled between a respective pair of sense amplifiers, and each latch is configured to output a data value that indicates a respective timing mismatch between outputs of the respective pair of sense amplifiers; and determining an entropy ratio for the particular address, wherein the entropy ratio is equivalent to a ratio of a first number of latches that output a first data value to a second number of latches that output a second data value.

主权项

1. A method of secure key generation for a semiconductor device, the method comprising:
writing a predetermined write pattern to a particular address of a volatile memory of the semiconductor device, wherein the volatile memory comprises a plurality of bit lines; reading data from the particular address while applying a first set of operating variables to the volatile memory, subsequent to the writing; sensing a first plurality of timing mismatches during the reading, wherein
a plurality of sense amplifiers are coupled to the plurality of bit lines,each latch of a plurality of latches is coupled between a respective pair of the plurality of sense amplifiers, andeach latch is configured to output one of a first data value and a second data value to indicate a respective timing mismatch between outputs of the respective pair of sense amplifiers; and determining an entropy ratio for the particular address, wherein
the entropy ratio is associated with the first set of operating variables, andthe entropy ratio is equivalent to a ratio of a first number of latches that output the first data value to a second number of latches that output the second data value during the sensing.