ACTIVE REGIONS WITH COMPATIBLE DIELECTRIC LAYERS

摘要

A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.

主权项

1. A method of fabricating a non-planar semiconductor device, the method comprising:
forming a semiconductor fin protruding from and continuous with a bulk crystalline semiconductor substrate; forming an isolation layer laterally adjacent to a lower portion of the semiconductor fin, wherein an upper portion of the semiconductor fin extends above the isolation layer, the upper portion of the semiconductor fin having a top surface and laterally adjacent sidewall surfaces; oxidizing outermost portions of the top surface and laterally adjacent sidewall surfaces of the upper portion of the semiconductor fin, the oxidizing forming an oxide layer on the top surface and laterally adjacent sidewall surfaces of the upper portion of the semiconductor fin; depositing a gate material on the oxide layer on the top surface and laterally adjacent sidewall surfaces of the upper portion of the semiconductor fin; patterning the gate material and the oxide layer to form a gate electrode on a gate dielectric layer on a portion of the top surface and laterally adjacent sidewall surfaces of the upper portion of the semiconductor fin; removing a portion of the upper portion of the semiconductor fin; and forming a replacement semiconductor fin upper portion comprising a semiconductor material different than the bulk crystalline semiconductor substrate, wherein the gate dielectric layer is on a channel region of a top surface and laterally adjacent sidewall surfaces of the replacement semiconductor fin upper portion.