CO-INTEGRATION OF TENSILE SILICON AND COMPRESSIVE SILICON GERMANIUM

摘要

Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

主权项

1. An integrated circuit comprising:
a silicon substrate; a compressive SiGe active layer on the silicon substrate; a p-type FinFET formed in the compressive SiGe active layer; a strain-relaxed SiGe region inlaid in the silicon substrate; a tensile silicon active layer on the strain-relaxed SiGe region and adjacent to the compressive SiGe active layer; an n-type FinFET formed in the tensile silicon active layer; and electrically insulating regions positioned between the p-type and n-type FinFETs, and between the strain-relaxed SiGe region and the silicon substrate.