| 发明名称 |
SEMICONDUCTOR STRUCTURE WITH ALIGNING MARK AND METHOD OF FORMING THE SAME |
| 摘要 |
The present invention provides a semiconductor structure comprising a wafer and an aligning mark. The wafer has a dicing region which comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. The aligning mark is disposed in the dicing region, wherein the alignment mark is a mirror symmetrical pattern. The aligning mark comprises a plurality of second patterns in the middle region and a plurality of third patterns disposed in peripheral region, wherein each third pattern comprises a plurality of lines, and a width of the line is 10 times less than a width of the L-shapes. The present invention further provides a method of forming the same. |
| 申请公布号 |
US2017062349(A1) |
申请公布日期 |
2017.03.02 |
| 申请号 |
US201514836947 |
申请日期 |
2015.08.26 |
| 申请人 |
UNITED MICROELECTRONICS CORP. |
发明人 |
Wang Ying-Chiao;Hung Yu-Hsiang;Lin Chao-Hung;Fu Ssu-I;Hsu Chih-Kai;Jenq Jyh-Shyang |
| 分类号 |
H01L23/544;H01L21/311;H01L21/033;H01L21/28 |
主分类号 |
H01L23/544 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A semiconductor structure, comprising:
a wafer having a dicing region which comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region; an aligning mark disposed in the dicing region, wherein the alignment mark is a mirror symmetrical pattern and comprises:
a plurality of second patterns in the middle region; anda plurality of third patterns disposed in peripheral region, wherein each third pattern comprises a plurality of lines, and a width of the line is 10 times less than a width of the second pattern. |
| 地址 |
Hsin-Chu City TW |
