Stacked Clock-Generation Circuit

摘要

An electronic circuit is disclosed for dividing the frequency of a periodic signal, wherein at least one of the memory elements is arranged with its output terminal connected to the input terminal of another memory element wherein the electronic circuit is configured to generate an output signal having a smaller fundamental frequency than the clock signal at at least one of the output terminals. Each memory element is configured to change and hold a voltage at the output terminal based on a voltage at the input terminal at times controlled by a clock signal received at the clock terminal. At least two of the memory elements are stacked in the sense that the bottom terminal of a first memory element is connected to the top terminal of a second memory element to enable the charge to flow from the first memory element to the second memory element.

主权项

1. An electronic circuit for dividing a frequency of a periodic signal, comprising
a plurality of memory elements, each memory element comprising an input terminal, an output terminal, a top voltage terminal, a bottom voltage terminal, and a clock terminal, wherein at least one of the memory elements is arranged with its output terminal coupled to the input terminal of another memory element wherein the electronic circuit is configured to generate an output signal having a smaller fundamental frequency than the clock signal at at least one of the output terminals; wherein each memory element is configured to change and hold a voltage at the output terminal based on a voltage at the input terminal at times controlled by a clock signal received at the clock terminal, by drawing a charge from the top voltage terminal to the output terminal or drain the charge from the output terminal to the bottom voltage terminal; and wherein at least two of the memory elements are stacked in the sense that the bottom terminal of a first memory element is connected to the top terminal of a second memory element to enable the charge to flow from the first memory element to the second memory element.