发明名称 EFFICIENT ENCODING AND DECODING ARCHITECTURE FOR HIGH-RATE DATA TRANSFER THROUGH A PARALLEL BUS
摘要 System, methods, and apparatus are described that facilitate transmission/reception of data over a multi-line parallel bus. In an example, the apparatus selects from a sequential series of data bits a plurality of data bits for transmission over a plurality of parallel bus lines. For each bus line of the plurality of parallel bus lines, the apparatus compares a state of a current data bit selected for transmission on a current bus line during a current clock cycle with one or more conditions related to the current bus line or at least one bus line adjacent to the current bus line, wherein the one or more conditions includes a state of two data bits respectively transmitted on two bus lines adjacent to the current bus line during a previous clock cycle, and determines whether to transmit the current data bit on the current bus line based on the comparison.
申请公布号 WO2017034754(A1) 申请公布日期 2017.03.02
申请号 WO2016US44592 申请日期 2016.07.28
申请人 QUALCOMM INCORPORATED 发明人 KUDEKAR, Shrinivas;NIESEN, Urs
分类号 G06F13/42 主分类号 G06F13/42
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