| 摘要 |
A content addressable memory device includes a first memory cell having three programmable resistive elements coupled in parallel. The first terminals of the first, second, and third programmable resistive elements are coupled to a first node, the second terminal of the first programmable resistive element coupled to a first source line voltage, the second terminal of the second programmable resistive element coupled to a second source line voltage, and the second terminal of the third programmable resistive element coupled to a first supply voltage. A first access transistor includes a first current electrode coupled to a bit line; a second current electrode coupled to the first node, and a control electrode coupled to a word line. A match line transistor includes a first current electrode coupled to a match line; a second current electrode coupled to a second supply voltage and a control electrode coupled to the first node. |
