Sensing scheme for high speed memory circuits with single ended sensing

摘要

A circuit detects values stored in bit cells of a memory circuit, for example, a memory circuit with single ended sensing. The circuit injects a charge into a bit line coupled to a bit cell to detect the value stored in the bit cell. A level detector detects the voltage level of the bitline as the charge in injected in the bitline. The sensing circuit determines the bit value stored during the charge injection phase. If the bitline voltage reaches above a high threshold voltage level as the charge in injected in the bitline, the circuit determines that the bit cell stores a first bit value (for example, bit value 1.) If the bitline voltage stays below a low threshold voltage level as the charge in injected in the bitline, the circuit determines that the bit cell stores a second bit value (for example, bit value 0).

主权项

1. A method of detecting a value stored in a bit cell of a read only memory (ROM) array, comprising:
receiving a pre-charge signal to inject charge into a bitline coupled to the bit cell of a plurality of bit cells connected to a word line, each bit cell configured to store one of a first bit value or a second bit value; responsive to detecting by a level detector that a voltage level of the bitline stays below a first threshold voltage level during the injection of the charge into the bitline, generating an inverter output signal at an output of an inverter based on the voltage level of the bitline received at an input of the inverter to cause a positive feedback circuit to output a first voltage value indicating that the bit cell stores the first bit value; and responsive to detecting by the level detector that the voltage level of the bitline exceeds a second threshold voltage level higher than the first threshold voltage level during the injection of the charge into the bitline, determining that the bit cell stores the second bit value; wherein the voltage level of the bitline increases above a first voltage level during the injection of the charge into the bitline responsive to the voltage level of the bitline staying below the first threshold voltage level during the injection of the charge into the bitline, the first voltage level lower than the first threshold voltage level; and the voltage level of the bitline decreases below the first voltage level after the injection of the charge into the bitline responsive to the voltage level of the bitline staying below the first threshold voltage level during the injection of the charge into the bitline.