发明名称 |
Compact memory device of the EEPROM type with a vertical select transistor |
摘要 |
Integrated non-volatile memory device includes an integrated memory cell of the EEPROM type with a floating-gate transistor and a selection transistor connected in series between a source line and a bit line, and a programming circuit for the memory cell. The selection transistor is connected between the floating-gate transistor and the source line. The programming circuit is configured for programming the at least one memory cell with a programming voltage split between a positive voltage and a negative voltage. |
申请公布号 |
US9583193(B2) |
申请公布日期 |
2017.02.28 |
申请号 |
US201514864354 |
申请日期 |
2015.09.24 |
申请人 |
STMicroelectronics (Rousset) SAS |
发明人 |
Tailliet François |
分类号 |
G11C11/34;G11C16/04;G11C16/14;G11C16/26;G11C16/10;G11C16/12;H01L27/115 |
主分类号 |
G11C11/34 |
代理机构 |
Slater Matsil, LLP |
代理人 |
Slater Matsil, LLP |
主权项 |
1. An integrated non-volatile memory device, comprising:
a source line; a bit line; an EEPROM-type memory cell disposed within a semiconductor substrate, the EEPROM-type memory cell comprising a floating-gate transistor and a selection transistor coupled in series between the source line and the bit line, the selection transistor comprising a vertical MOS transistor that is connected between the floating-gate transistor and the source line; and a programming and erasing circuit coupled to the EEPROM-type memory cell, the programming and erasing circuit configured to program the EEPROM-type memory cell with a programming voltage split between a positive voltage and a negative voltage, and configured to electronically erase the EEPROM-type memory cell, wherein the programming voltage is applied between a control gate of the floating-gate transistor and the bit line. |
地址 |
Rousset FR |