Centralized variable rate serializer and deserializer for bad column management

摘要

A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer circuit is connected to a data bus and the access circuitry to convert data between a (word-wise) serial format on the bus and (multi-word) parallel format for the access circuitry. Column redundancy circuitry is connect to the serializer/deserializer circuit to provide defective column information about the array. In converting data from a serial to a parallel format, the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. In converting data from a parallel to a serial format the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column.

主权项

1. A memory circuit comprising:
a first array of non-volatile memory cells formed along a plurality of word lines and a plurality of columns, wherein the columns are subdivided into a plurality of N divisions, each division formed of a plurality of contiguous columns, where the word lines span all of the columns of the array; a first plurality of N sets of access circuitry, each connectable to the columns of a corresponding division of the first array, wherein N is an integer greater than one; a serializer circuit connected to the first plurality of sets of access circuitry to receive in parallel each of N words of data from a corresponding one of the first plurality of sets of access circuitry and connected to a data bus to transfer thereto the received data in a word-wide serial data format according to a first clock signal; and column redundancy circuitry connected to the serializer circuit to provide defective column information thereto, whereby, in converting data from a parallel to a serial format the serializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location thereof corresponds to a defective column.